You can download the full PDF directly from JEDEC (registration required, but free): Download JESD79-4D at JEDEC.org

Standards aggregators like Accuris (formerly IHS Markit) and GlobalSpec provide the document for purchase or as part of a subscription.

: Memory bandwidth remains a principal bottleneck in high-performance computing. Problem : Strict power grids and high data rates (

This created a scheduling puzzle for CPU memory controllers. If a controller issues a read command to Bank Group 0, it must wait a specific number of cycles before issuing a command to Bank Group 1 to avoid a "bus collision" on the internal data paths.