Synopsys Timing Constraints And Optimization User Guide 2021 [2021] -

: Use create_clock for primary clocks and create_generated_clock for derived clocks (e.g., dividers or multipliers).

create_clock -name clk -period 10 -waveform 0 5 set_input_delay -max 3 -clock clk [get_ports input_port] set_output_delay -max 2 -clock clk [get_ports output_port] synopsys timing constraints and optimization user guide 2021

Even if you're on a newer tool version, the 2021 guide explains why certain constraints behave the way they do during optimization (e.g., priority of path exceptions, clock latency updates). priority of path exceptions

: Flags incorrect or incomplete SDC entries that could lead to silicon failure. synopsys timing constraints and optimization user guide 2021